Nios II Processor-Based Hardware/Software Co-Design of the JPEG2000 Standard

JPEG2000 is a recently standardized image compression algorithm that provides significant enhancements over the existing JPEG standard. JPEG2000 differs from widely used compression standards in that it relies on discrete wavelet transform (DWT) and uses embedded bit plane coding of the wavelet coefficients [1]. Due to the bit-oriented processing techniques used in the standard, full implementation via software is inefficient, making embedded processing slow on standard microprocessors. Possible applications, such as scanners and printers, require a reasonable processing speed, which may be difficult to achieve using existing embedded processors. On the other hand, a full hardware implementation may not utilize the flexibility available in the standard. To improve the speed of the JPEG2000 algorithm while maintaining flexibility, we investigate the use of a co-design approach, using hardware acceleration for the bit-oriented and digital signal processing (DSP) tasks while leaving packet formation, code-stream formatting, and manipulation to software.